This invention relates to a complementary semiconductor device having a high operation speed and which is not affected by external electrical noise. More particularly, it relates to a complementary semiconductor integrated circuit (IC) device including two types of metal-insulator-semiconductor (MIS) field effect transistors (FETs) of one conductivity type, whereby the FETs of one type have a high switching speed, and those of the other type have a capability of suppressing the latchup effect of the device, each type of the FETs being selectively used depending on the needs for particular circuits.
Hereafter, a CMOS (complementary metal-oxide-semiconductor) FET is described as a representative device of the CMIS FETs.
As the demand for high packing density in semiconductor devices increases, the level of power consumption per device has been going up, raising a serious heat dissipation problem. In view of this, CMOS type ICs are very advantageous due to their particularly low power consumption. Generally, the CMOS IC is formed, for example, in an n-type silicon substrate of low dopant concentration, and comprises a p-channel type MOS FET and an n-type channel MOS FET. The former is formed directly in the substrate and the latter is formed in a p-type well region which is formed in the substrate. The well region is defined as a diffusion region formed in a semiconductor substrate, which has a higher dopant concentration than that of the substrate and a larger diffusion depth than that of the other diffusion regions formed in the same substrate.
The low power consumption of a CMOS device is realized by the operation of its basic inverter circuit composed of a pair of MOS FETs, namely an n-type channel MOS FET and a p-type channel MOS FET, wherein power source current flows only during a dynamic state, namely, the switching period from a high signal level to a low signal level or vice versa. In a static state or a standby state, one of the FETs is always in an OFF state, blocking the current flowing from source to ground.
In spite of the above advantage, the CMOS device has several inherent problems, such as a short channel effect, large junction capacitance, latchup effect, etc. When the structure of ICs becomes miniaturized, these problems become serious. These problems will be reviewed briefly in the following.
In order to increase the switching speed and the packing density of a semiconductor device, the gate channel length of the FETs formed in the device has been increasingly shortened. However, this shortened channel length tends to result in a "punch-through" effect. The effect is derived from extension of depletion regions around the source region and drain region of an MOS FET, generated by the application of a voltage to both regions. When both extended depletion regions come close to each other, a voltage breakdown might occur. This is referred to as a "punch-through" effect.
Generally, in a typical CMOS IC, a semiconductor substrate of low concentration is used in order to reduce the junction capacitance of an FET formed therein in order to attain switching speed. This prompts the extension of the depletion regions which leads to the occurrence of a punch-through effect. For preventing this problem, a CMOS IC having twin-tub well regions has been introduced, wherein an n-type channel FET and a p-type channel FET, for example, are formed respectively in a p-type well and an n-type well, the wells being formed in an n.sup.- -type substrate. Since a well region contains a dopant concentration higher than that of the substrate by approximately one order, the extension of the depletion regions around the diffusion regions of FETs is reduced to prevent the punch-through effect thereof. In addition, the latchup effect is also reduced by the presence of the well regions by reducing the resistivity of the substrate.
On the other hand, in the twin-tub structure, each diffusion region is facing each well region of a high dopant concentration, providing the respective FETs with large junction capacitances, resulting in the reduction of switching speed of the associated semiconductor device. In order to overcome this problem, a modified twin-tub structure of a CMOS having a higher switching speed has been proposed by the inventor herein in a Provisional Publication of Japanese Patent Application laid open to public inspection, TOKU-KAI-SHO 60-123055, July 1, 1985.
FIG. 1 is a cross-sectional view of an example of the modified structure of the CMOS FETs formed in an n.sup.- -type silicon substrate, having twin-tub CMOS transistors. In the silicon substrate 1, there is formed a p-type well region 2, having an n-channel MOS transistor n-Tr disposed therein. The transistor n-Tr comprises an n.sup.+ -type source region 3, an n.sup.+ -type drain region 4, a gate insulator 5 and a gate electrode 6. Further, in the n.sup.- -type silicon substrate 1, a p-channel MOS transistor p-Tr having a modified structure is formed. The p-Tr comprises a p.sup.+ -type source region 7, a p.sup.+ -type drain region 8, a gate insulator 5, a gate electrode 6 and a sub-well region 9. Also, in the substrate 1, there are formed, as illustrated in FIG. 1, field insulator layers 10 defining transistor regions therebetween, n.sup.+ -type channel stoppers 11 and p.sup.+ -type channel stoppers 12, and an n.sup.+ -type contact 14 for the substrate 1 and a p.sup.+ -type contact 15 for the well region 2.
It is the feature of the modified structure of the transistor p-Tr, that the n-type sub-well region 9 is formed beneath the gate insulator 5 such that a part of the p.sup.+ -type source region 7 and the p.sup.+ -type drain region 8 directly contact the n.sup.- -type substrate 1. Thus the junction capacitances of the source region 7 and the drain region 8 are substantially reduced from those of a conventional twin-tub CMOS FET, resulting in an improvement in the switching speed of the device. Furthermore, the sub-well region 9 acts adversely to the extension of the depletion regions around the source region 7 and the drain region 8, thereby reducing the punch-through effect. However, an MOS FET with the modified twin-tub structure has another disadvantage in that a latchup effect tends to occur more easily as compared with the prior art twin-tub CMOS transistor.
The latchup effect is described briefly referring to FIG. 2, which is a schematic cross-sectional view of an ordinary CMOS IC device. In FIG. 2, a circuit diagram of an inverter of the CMOS device and its equivalent circuit diagram are given, illustrating parasitic transistors and resistances created by elements of the IC device. In an n.sup.- -type substrate n.sub.sub, a p-type well region p.sub.well and a p-channel MOS FET p-Tr are formed. The p-type channel FET p-Tr has a p-type source region S.sub.p, a p-type drain region D.sub.p, a gate electrode G.sub.p and a gate insulator. In the p-type well region, an n-type channel FET n-Tr is formed having an n-type source region S.sub.n, an n-type drain region D.sub.n, a gate electrode G.sub.n and a gate insulator. Reference characters +Vdd, Vss, IN and OUT respectively denote a power source terminal, a ground terminal, an input terminal and an output terminal. In this configuration, a parasitic pnp transistors (pnpTr) is created by a combination of S.sub.p, n.sub.sub and p.sub.well and a parasitic npn transistor (npnTr) is created by a combination of S.sub.n, p.sub.well, and n.sub.sub. Between other terminals, parasitic resistances R.sub.1 and R.sub.2 are created by the inherent resistance of the parts of the associated devices. Along current paths, as shown in FIG. 2 with dotted lines, a thyristor is formed by these parasitic elements, causing a latchup effect. For example, if a large noise current from an external noise source, sufficient to turn the parasitic transistor npnTr "ON", flows through the drain region D.sub.n, a source current starts flowing from the +Vdd terminal to the ground terminal Vss through the parasitic resistances R.sub.1 and R.sub.2. When the resulting voltage drop across the parasitic resistance R.sub.2 exceeds the base voltage of the parasitic transistor pnpTr, the transistor becomes conductive, providing a current flow to the base of the parasitic transistor npnTr, resulting in an increase in the base current making the npnTr more conductive. This is a kind of positive feedback loop composed of the pnpTr and npnTr, bringing the parasitic thyristor into an "ON" state. As a result, a large current keeps flowing from the source terminal +Vdd to the ground terminal Vss, even though the exterior noise signal which triggered the current is eliminated, the current can be stopped only by turning off the power supply. If the current is not stopped, the whole semiconductor device will be damaged by the current. This phenomenon is referred to as a latchup effect. One of the effective methods for eliminating the latchup effect is to reduce the resistance of the parasitic resistance R.sub.2.
With a modified CMOS FET described above, the sub-well region 9 having a deep diffusion region with a high dopant concentration, serves to reduce the latchup effect to some degree, however, its capability for suppressing the latchup effect is unsatisfactory in comparison with that of a conventional MOS FET formed in a complete well region. In other words, the parasitic resistance R.sub.2 of the modified CMOS FET shown in FIG. 1 is not reduced satisfactorily, even though the transistor has a high switching speed as described above.